Description: Client Job Title: FPGA Design Verification Engineer Job Title: Technical Lead II ... highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... will work closely with design engineers to develop and execute verification pla
26 days ago
Description: Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite) ... FPGA design principles and architectures. Proficiency in System Verilog and UVM verification ...
7 days ago
Description: Job Title: Hardware/FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite) ... FPGA design principles and architectures. Proficiency in System Verilog and UVM verification ...
28 days ago
... , RTL design principles and architecturesProficiency in System Verilog and UVM verification methodologyExperience ... -standard verification tools (e.g., QuestaSim, Synopsys VCS, Haps)Experience with high-speed I/O design ...
11 days ago
Description: Job Title: FPGA/Design Verification Engineer Location: Mountain View, CA (Onsite) ... FPGA design principles and architectures. Proficiency in System Verilog and UVM verification ...
12 days ago
Description: Title-FPGA Verification Engineer Location-Mountain View, CA Duration- ... -Onsite Must Have Skills FPGA Verification Engineer Skill 1 8 + Years of in FPGA ... FPGA design principles and architectures. Proficiency in System Verilog and UVM verification ...
4 days ago
Description: Position: FPGA Verification Engineer Location: Mountain View, ... design principles and architectures. Proficiency in System Verilog and UVM verification ... methodology. Experience with industry-standard verification tools (e.g., ...
25 days ago
$90
$95
an hour
Description: Mixed Signal Model Verification Engineer San Jose, CA (Hybrid) 3 + Months $ ... SystemVerilog, including real number modeling. Verification Flow: Strong understanding of HDL ... background in analog integrated circuit design and read
26 days ago
... : We are looking for Board Verification Engineer for our client in Markham ... , ON Job Title: Board Verification Engineer Job Location: Markham, ON Job ... -functional engagement from the various design teams, program leads and, program ...
26 days ago
... maintain comprehensive testing schedules for Design Verification (DV) and Validation activities, collaborating ... , and within project managemThe Project Engineer will be a key member of ...
22 days ago
Description: Position Title: Electrical Design Verification Test (EDVT) Engineer Location: Sunnyvale, CA- 100% onsite ... addition to networking products. This engineer
25 days ago
Description: Role: Silicon Design Package Engineer Location:Santa Clara, CA ... highly specialized in semiconductor packaging design, requiring strong EDA tool ... Technical Expertise: Multi-layer package design experience. Understanding of substrate manufacturing ...
19 days ago
Description: Silicon Design Package Engineer Location Santa Clara, CA (Onsite ... highly specialized in semiconductor packaging design, requiring strong EDA tool ... Expertise: Multi-layer package design experience. Understanding of substrate manufacturing ...
27 days ago
Description: Role: GenDesign / Inverse Design Ai Engineer Location: Santa Clara, CA We ... are seeking a Generative AI (GenAI) Design Engineer to join our team and ... such as content creation, product design, and intelligent automation.Develop forward ...
29 days ago
... highly motivated and skilled FPGA Verification Engineer to join our dynamic team ... responsible for the verification of complex FPGA designs, ensuring their functionality ... work closely with design engineers to develop and execute verification plans, identify ...
29 days ago
... Engineer to join our team, focusing on the software stack for Design Verification ... software prototypes for early "h/w + s/w co-designs," build validation test cases in ...
13 days ago
... Engineer to join our team, focusing on the software stack for Design Verification ...
13 days ago
... maintain comprehensive testing schedules for Design Verification (DV) and Validation activities, collaborating ... within project managem The Project Engineer will be a key member of ...
20 days ago
... aLead Package Design Engineer, you will take ownership of package design and layout ... performance optimization, design for manufacturing, and sign-off verification. You will ... also , guiding best practices in APD, reviewing design ...
12 days ago
... outstanding Camera Image Quality Test Engineer who has a good understanding of ... and real world image quality verification to help deliver the best ...
7 days ago