Description: Title:Silicon Verification Engineer 5Location: Mountain View,CA(Hybrid) ... Chip/full system level ASIC Verification skills, and debug skills a must ...
15 days ago
... - Define, document, and implement a UVM verification environment including agents and scoreboards ... , checkers, coverage, and other verification collateral - Run tests on RTL ... fixes - Support post-silicon verification activities of the products working ...
3 days ago
Description: job summary: Design verification activities to design quality into ...
29 days ago