Description: Position: FPGA Verification Engineer Location: San Jose, CA - Onsite ... Job Description & Responsibilities Own verification of entire FPGA design used ... and interact with design engineers to identify verification scenariosCreate test plans, ...
a day ago
Description: Job Title: GPU Design Verification Engineer Location: San Jose, CA (Onsite) ... are seeking a highly skilled Design Verification Engineer to join our team at ... be on developing and executing verification plans, creating testbenches, and debugging ...
28 days ago
... are seeking a highly skilled Design Verification Engineer to join our team.The ... be on developing and executing verification plans, creating testbenches, and debugging ... . Responsibilities Develop and execute comprehensive verification plans for GPU
29 days ago
Description: Role: Senior/Staff VLSI Engineer Ethernet FEC DV Duration: 12+ ... skilled and motivated VLSI Design Verification Engineer with deep expertise in Forward ... role, you will own the verification of advanced FEC IP cores ...
14 hours ago
... : Analog and Mixed-Signal Layout Engineer Job Description The candidate should ... work with both design engineers and mask design engineers in remote locations ...
24 days ago
Description: ResponsibilitiesOwn verification of entire FPGA design ... and interact with design engineers to identify verification scenariosCreate test plans, constrained ... -random verification environments, test cases, regressions, and ...
24 days ago
... Summary:Drive the pre-silicon verification of next-generation PCIe Switch ...
7 days ago
Description: Salary Verbias for San Jose, CA: GlobalLogic estimates the starting pay range for this role to be performed within the USA to be $135K to $155K and reflects base salary only and does not include additional performance-linked variable ...
7 days ago
Description: JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, ...
8 days ago
... IP is hiring for a Verification Engineer to join their high-performance ... team! Responsibilities include: - Developing verification environments using System Verilog and ... UVM - Designing verification components and behavioral models - ...
23 days ago
... Description: Position: FPGA Verification Contractor Location: San Jose ... Description & Responsibilities Own verification of theentire FPGA designused ... engineersto identify verification scenariosCreatetest plans,constrained-random verification environments,test ...
23 days ago
$50
$55
an hour
Description: Locals Only! Emulation & Prototyping Engineer (2 Openings) San Jose, CA - Hybrid ( ... emulation models Perform pre-silicon verification & SoC bri
2 days ago
... a highly skilled and motivated DFT Engineer with 6+ years of experience to ... will work closely with design, verification, and product engineering teams to ...
14 days ago
... the position of Signal Integrity Engineer to help design and build ... Platform Solutions. The Signal Integrity Engineer will play a critical role as ... digital PCB designs, simulation, lab verification, and troubleshooting signal integrity issues o
21 days ago
... the position of Signal Integrity Engineer to help design and build ... Platform Solutions. The Signal Integrity Engineer will play a critical role as ... digital PCB designs, simulation, lab verification, and troubleshooting signal integrity issues
21 days ago