... in IC package design and development. Proficiency with Cadence Allegro Package Designer. Experience in ... Wire bond, Flip chip Substrate designs. Hands ... the impact of the substrate design to support CoWoS. Knowledge ...
24 days ago
... resume along with LinkedIn Position : Package Designer Location: San Jose, CA Duration ... experienced Packaging Designer to develop creative and cost-effective IC package designs. Job ...
6 days ago
Description: Title: Package Designer (Onsite - San Jose)Experience: 5+ Years ... experienced Packaging Designer to develop creative and cost-effective IC package designs. Job ...
24 days ago
Description: Job Title: Package Designer Location: San Jose CA / Chandler, ... strategies and via structures. Substrate design experience for RF, digital, high ...
17 hours ago
Description: Job Title: Package Designer Location: San Jose CA / Chandler, ... strategies and via structures. Substrate design experience for RF, digital, high ...
3 days ago
Description: Job Title: Package Designer Location: San Jose CA / Chandler, ... strategies and via structures. Substrate design experience for RF, digital, high ...
4 days ago
Description: Job Title: Package Designer Location: San Jose CA / Chandler, ... strategies and via structures. Substrate design experience for RF, digital, high ...
5 days ago
Description: Job Title: Package Designer Location: San Jose CA / Chandler, ... strategies and via structures. Substrate design experience for RF, digital, high ...
6 days ago
Description: Job Title: Package Designer Location: San Jose CA / Chandler, ... strategies and via structures. Substrate design experience for RF, digital, high ...
20 days ago
... combination of pre-silicon and post-silicon expertise to provide ... turnkey solution for silicon bring-up and ... silicon and system testing labs. We offer Turnkey ASIC Solutions from design ... to packaged parts, leveraging strong ...
28 days ago
Description: Role: Hardware Systems Design Engineer Location: San Jose, CA ( ... ) AI/ML processors. Board-Level Design: Lead PCB layout and SI ... Bring-up: Design boards intended for ASIC bring-up and post-silicon
5 days ago
Description: Position: Hardware Systems Design Engineer Location: San Jose, CA ( ... -up: Design boards intended for ASIC bring-up and post-silicon validation ...
5 days ago
Description: Job Title: UI/UX Designer Location: San Jose, CA Years ... skilled UI/UX Designer with a strong emphasis on UX Design to join ... a deep understanding of user centered design principles and methodologies. You will ...
6 days ago
$70
$100
an hour
Description: PCB Designer - Cadence Allegro Experience Location: Hybrid ... experienced PCB Designer with expertise in Cadence Allegro PCB design tools to ... play a key role in the design, layout, and optimization of Printed ...
28 days ago
Description: Trainee AI Web Designer Our client is a fast-growing ... join as Trainee AI Web Designers. This is your chance to ... a high-income career in web design. What You ll Do Learn ... how to use powerful AI design tools to create professional, modern ...
14 days ago
... skilled UI/UX Designer with a strong emphasis on UX Design to join ... a deep understanding of user centered design principles and methodologies. You will ...
10 days ago
Description: Package Design Engineer in the US, please ... , Cadence, PLA knowledge Multiple layers package design (8+) experience Understanding of substrate manufacturing ... assembly rule Possess Flip Chip Package Design Concept Good communication skill. May ...
6 days ago
... experienced packaging designer to develop innovative and cost-effective packaging designs. JOB ... strategies, and via structures.Substrate design experience for RF, digital, high ...
19 days ago
... package design (8+) experienceUnderstanding of substrate manufacturing design rule and assembly rulePossess Flip Chip Package Design ...
5 days ago
Description: Position: IC Design Engineer Location: San Jose, CA & ... looking for an experienced IC Package Design Engineer to develop creative, efficient ... Description: Create Netlists and BGA designs as per input specifications. Conduct ...
25 days ago
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