... Description: Job Title: FPGA Design Verification Engineer/Technical Lead II - VLSI Location: ... design principles, and architectures. Proficiency in SystemVerilog and UVM verification ... operating systems. Proficiency with verification tools such as QuestaSim, ...
17 days ago
... Description: Role summary Seeking a Senior Design Verification Engineer with 8+ years of experience ... in IP and subsystemlevel verification using SystemVerilog and UVM. The ... silicon. Key responsibilities - Own verification of one or more IPs ...
2 days ago
... , We are looking for SOC Design Verification Engineer, and the following below ... your updated resume. Role: SOC Design Verification Engineer Work location: Santa Clara ...
25 days ago
... performance validation.Identify and resolve design issues in collaboration with ... teams.Participate in design reviews and contribute to verification strategy.Stay current ... verification tools and methodologies.Strong knowledge of FPGA, ASIC, and RTL design ...
27 days ago
... following areas along with functional verification-SV Assertions, Formal, Emulation.Experience ...
24 days ago
Description: Urgent Opening:DesignVerificationEngineer Job Title:DesignVerificationEngineer Experience: 10+ years Location: San Jose, CA (or other US locations) Job Type: Full-time/Contract KeyRequirements: - Experience working on Subsystems on a Chip ( ...
23 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
6 hours ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology)Familiarity with industry ... -standard verification tools (e.g., QuestaSim, ...
2 days ago
... Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years of FPGA verification ... with UVM (Universal Verification Methodology) Familiarity with ... industry-standard verification tools (e.g., QuestaSim, ...
6 days ago
... a highly motivated and skilled FPGA Verification Engineer to join our dynamic ... be responsible for the verification of complex FPGA designs, ensuring their functionality ... work closely with design engineers to develop and execute verification plans, identify ...
16 days ago
... a highly motivated and skilled FPGA Verification Engineer to join our dynamic ... be responsible for the verification of complex FPGA designs, ensuring their functionality ... work closely with design engineers to develop and execute verification plans, identify ...
17 days ago
... a highly motivated and skilled FPGA Verification Engineer to join our dynamic ... be responsible for the verification of complex FPGA designs, ensuring their functionality ... work closely with design engineers to develop and execute verification plans, identify ...
22 days ago
... Verification Engineer to verify complex FPGA designs. You will develop and execute verification ... performance validation.Identify and resolve design issues in collaboration with ... teams.Participate in design reviews and contribute to verification strategy.Stay ...
a month ago
... a highly motivated and skilled FPGA Verification Engineer to join our dynamic ... be responsible for the verification of complex FPGA designs, ensuring their functionality ... work closely with design engineers to develop and execute verification plans, identify ...
14 days ago
... CA Job Title: Testbench/Verification Engineer Job Location: Santa ... Range: $70hr - $86hrThe Verification Engineer will be responsible for ... the simulation of complex designs at component or subsystem ... strong collaboration with design, architecture, and perform
25 days ago
... Verification Engineer to verify complex FPGA designs. You will develop and execute verification ... performance validation.Identify and resolve design issues in collaboration with ... teams.Participate in design reviews and contribute to verification strategy.Stay ...
30 days ago
... performance validation.Identify and resolve design issues in collaboration with ... teams.Participate in design reviews and contribute to verification strategy.Stay current ... verification tools and methodologies.Strong knowledge of FPGA, ASIC, and RTL design ...
29 days ago
Description: FPGA Verification Engineer Santa Clara, ... Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + ... motivated and skilled FPGA Verification Engineer to join our ... responsible for the verification of complex FPGA designs, ensuring their ...
8 days ago
Description: FPGA Verification Engineer-Santa Clara, ... Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + ... motivated and skilled FPGA Verification Engineer to join our ... responsible for the verification of complex FPGA designs, ensuring their ...
15 days ago
... : Role : FPGA Verification Engineer Location Santa Clara ... Areas Must Have Skills FPGA Verification Engineer Skill 1 8 + ... motivated and skilled FPGA Verification Engineer to join our ... responsible for the verification of complex FPGA designs, ensuring their ...
16 days ago
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